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VIPA SPEED7 CPU 313SCDPM - Page 140

VIPA SPEED7 CPU 313SCDPM
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Local
byte
Bit 7...0
10
n Bit 0: Gate counter 0 open (activated)
n Bit 1: Gate counter 0 closed
n Bit 2: Over-/underflow/end value counter 0
n Bit 3: Counter 0 reached comparison value
n Bit 4: Gate counter 1 open (activated)
n Bit 5: Gate counter 1 closed
n Bit 6: Over-/underflow/ end value counter 1
n Bit 7: Counter 1 reached comparison value
11
n Bit 0: Gate counter 2 open (activated)
n Bit 1: Gate counter 2 closed
n Bit 2: Over-/underflow/end value counter 2
n Bit 3: Counter 2 reached comparison value
n Bit 7 ... 4: reserved
Local double word 8 of OB 40 at frequency measurement
Local
byte
Bit 7...0
8
n Bit 0: Edge at I+0.0
n Bit 1: Edge at I+0.1
n Bit 2: Edge at I+0.2
n Bit 3: Edge at I+0.3
n Bit 4: Edge at I+0.4
n Bit 5: Edge at I+0.5
n Bit 6: Edge at I+0.6
n Bit 7: Edge at I+0.7
9
n Bit 0: Edge at I+1.0
n Bit 1: Edge at I+1.1
n Bit 2: Edge at I+1.2
n Bit 3: Edge at I+1.3
n Bit 4: Edge at I+1.4
n Bit 5: Edge at I+1.5
n Bit 6: Edge at I+1.6
n Bit 7: Edge at I+1.7
10
n Bit 0: End of measurement channel 0 (end of the
integration time)
n Bit 3 ... 1: reserved
n Bit 4: End of measurement channel 1 (end of the
integration time)
n Bit 7 ... 5: reserved
11
n Bit 0: End of measurement channel 2 (end of the
integration time)
n Bit 7 ... 1: reserved
VIPA System 300SDeployment I/O periphery
Diagnostic and interrupt > Process interrupt
HB140 | CPU-SC | 313-6CF13 | GB | 15-50 140

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