5.12.2 Function security
The CPUs include security mechanisms like a Watchdog (100ms)
and a parametrizable cycle time surveillance (parametrizable min.
1ms) that stop res. execute a RESET at the CPU in case of an error
and set it into a defined STOP state. The VIPA CPUs are developed
function secure and have the following system properties:
Event concerns Effect
RUN ® STOP general BASP (Befehls-Ausgabe-Sperre, i.e. com-
mand output lock) is set.
central digital outputs The outputs are disabled.
central analog outputs The outputs are disabled.
n Voltage outputs issue 0V
n Current outputs 0...20mA issue 0mA
n Current outputs 4...20mA issue 4mA
If configured also substitute values may be
issued.
decentral outputs Same behavior as the central digital/analog
outputs.
decentral inputs The inputs are cyclically be read by the
decentralized station and the recent values
are put at disposal.
STOP ® RUN res.
PowerON
general First the PII is deleted, then OB 100 is
called. After the execution of the OB, the
BASP is reset and the cycle starts with:
Delete PIO ® Read PII ® OB 1.
decentral inputs The inputs are once be read by the decen-
tralized station and the recent values are
put at disposal.
RUN general The program execution happens cyclically
and can therefore be foreseen: Read PII ®
OB 1 ® Write PIO.
PII: Process image inputs, PIO: Process image outputs
5.13 Overall reset
During the overall reset the entire user memory is erased. Data
located in the memory card is not affected. You have 2 options to ini-
tiate an overall reset:
n initiate the overall reset by means of the operating mode switch
n initiate the overall reset by means of the Siemens SIMATIC Man-
ager
You should always issue an overall reset to your CPU
before loading an application program into your CPU to
ensure that all blocks have been cleared from the CPU.
Overview
VIPA System 300SDeployment CPU 313-6CF13
Overall reset
HB140 | CPU-SC | 313-6CF13 | GB | 15-50 68
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