Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 63
UG482 (v1.9) December 19, 2016
Power Down
Generic Power-Down Capabilities
The GTP transceiver provides several power-down features that can be used in a wide variety of
applications. Table 2-25 summarizes these capabilities.
PLL Power Down
To activate the PLL0 power-down mode, the active-High PLL0PD signal is asserted. Similarly, to
activate the PLL1 power-down mode, the active-High PLL1PD signal is asserted. When either
PLL0PD or PLL1PD is asserted, the corresponding PLL is powered down. As a result, all clocks
derived from the respective PLL are stopped.
During initial configuration and power-on, PLL0/PLL1 must be powered down using the PLL0PD/
PLL1PD port until reference clock edges are detected. PLL0/PLL1 should be powered down if the
reference clock stops. For PLL0-based designs, when PLL1 is not used, PLL1PD can be tied High.
For PLL1-based designs, when PLL0 is not used, the PLL0PD can be tied High.
Recovery from this power state is indicated by the assertion of the corresponding PLL lock signal.
PD_TRANS_TIME_TO_P2 8-bit Hex Counter settings for programmable
transition time to P2 state for PCIe. The
recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
TRANS_TIME_RATE 8-bit Hex Counter settings for programmable
transition time when the rate is changed
using the [TX/RX]RATE pins for all
protocols including the PCIe protocol
(Gen2/Gen1 data rates). The recommended
value from the 7 Series FPGAs Transceivers
Wizard should be used.
RX_CLKMUX_PD 1-bit Binary The recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
TX_CLKMUX_PD 1-bit Binary The recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
Table 2-24: Power-Down Attributes (Cont’d)
Attribute Type Description
Table 2-25: Basic Power-Down Functions Summary
Function Controlled By Affects
PLL0 Control PLL0PD Powers down PLL0.
PLL1 Control PLL1PD Powers down PLL1.
TX Power Control TXPD[1:0] The TX of the GTP transceiver.
RX Power Control RXPD[1:0] The RX of the GTP transceiver.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600