Xilinx Virtex UltraScale+ FPGAs User Manual

Simulation
The simulaon environment and the test bench must fulll specic prerequisites before running
simulaon using the GTM_DUAL primives. For instrucons on how to set up the simulaon
environment for supported simulators depending on the used hardware descripon language
(HDL), see the latest version of the UltraScale+ GTM Transceivers Wizard LogiCORE IP Product
Guide (PG315) and Vivado Design Suite User Guide: Logic Simulaon (UG900).
The prerequisites for simulang a design with the GTM_DUAL primives are listed:
• A simulator with support for SecureIP models: SecureIP is an IP encrypon methodology.
SecureIP models are encrypted versions of the Verilog HDL used for implementaon of the
modeled block. To support SecureIP models, a simulator that complies with the encrypon
standards described in the Verilog language reference manual (LRM)—IEEE Standard for
Verilog Hardware Descripon Language (IEEE Std 1364-2005) is required.
• A mixed-language simulator for VHDL simulaon: SecureIP models use a Verilog standard. To
use them in a VHDL design, a mixed-language simulator is required. The simulator must be
able to simulate VHDL and Verilog simultaneously.
• An installed GTM transceiver SecureIP model
• The correct setup of the simulator for SecureIP use (inializaon le, environment variables).
• The correct simulator resoluon (Verilog).
Ports and Attributes
There are no simulaon-only ports on the GTM_DUAL primives. The GTM_DUAL primive has
aributes intended only for simulaon. The following table lists the simulaon-only aributes of
the GTM_DUAL primive. The names of these aributes start with SIM_.
Table 2: GTM_DUAL Simulation-Only Attributes
Attribute Type Description
SIM_RESET_SPEEDUP String If the SIM_RESET_SPEEDUP attribute is set to TRUE (default), an
approximated reset sequence is used to speed up the reset time for
simulations, where faster reset times and faster simulation times are
desirable. If the SIM_RESET_SPEEDUP attribute is set to FALSE, the
model emulates hardware reset behavior in detail.
SIM_DEVICE
String This attribute selects the simulation version to match different
versions of silicon. The default for this attribute is ULTRASCALE_PLUS.
Chapter 1: Transceiver and Tool Overview
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 10
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English