Chapter 1
Transceiver and Tool Overview
Introduction to the UltraScale
Architecture
The Xilinx
®
UltraScale™ architecture is the rst ASIC-class architecture to enable mul-hundred
gigabit-per-second levels of system performance with smart processing, while eciently roung
and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of
high-bandwidth, high-ulizaon system requirements by using industry-leading technical
innovaons, including next-generaon roung, ASIC-like clocking, 3D-on-3D ICs, mulprocessor
SoC (MPSoC) technologies, and new power reducon features. The devices share many building
blocks, providing scalability across process nodes and product families to leverage system-level
investment across plaorms.
Virtex
®
UltraScale+™ devices provide the highest performance and integraon capabilies in a
FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as
the highest on-chip memory density. As the industry's most capable FPGA family, the Virtex
UltraScale+ devices are ideal for applicaons including 1+ Tb/s networking and data center and
fully integrated radar/early-warning systems.
Virtex
®
UltraScale™ devices provide the greatest performance and integraon at 20 nm,
including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the
20 nm process node, this family is ideal for applicaons including 400G networking, large scale
ASIC prototyping, and emulaon.
Kintex
®
UltraScale+™ devices provide the best price/performance/wa balance in a FinFET
node, delivering the most cost-eecve soluon for high-end capabilies, including transceiver
and memory interface line rates as well as 100G connecvity cores. Our newest mid-range family
is ideal for both packet processing and DSP-intensive funcons and is well suited for applicaons
including wireless MIMO technology, Nx100G networking, and data center.
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 5