Xilinx Virtex UltraScale+ FPGAs User Manual

TX FEC
The Integrated KP4 Reed-Solomon Forward Error Correcon (RS-FEC) provides a robust mul-bit
error detecon/correcon algorithm that protects up to 2 x 58 Gb/s or 1 x 116 Gb/s electrical
and opcal links. This secon describes the operaon of the Integrated KP4 RS-FEC within the
UltraScale+™ device GTM transceivers.
KP4 FEC is based on the RS(544,514) code, which encodes message blocks of 5140 bits to
produce codewords of 5440 bits. For a detailed descripon of the RS-FEC sublayer in Ethernet,
including the denion of the KP4 FEC code, refer to clause 91 of the IEEE Standard for Ethernet
(IEEE Std 802.3-2015). The same FEC code is used in other standards such as OTN FlexO and
Interlaken.
The Integrated KP4 RS-FEC for each GTM dual is composed of two logical slices for each
channel. These can operate as two independent RS-FEC processing units at up to 58 Gb/s each,
or as one unied unit at up to 116 Gb/s. When operang at up to 116 Gb/s, data is transmied
and received over four virtual FEC lanes as described in IEEE 802.3-2015 clause 91. When
operang as 2 x 58 Gb/s, data can be transmied and received over two virtual FEC lanes per
58 Gb/s channel, or as a raw data stream (one virtual lane) with oponal PN scrambling for
backplane operaons. The general principle of operaon of the FEC is the same whichever mode
is chosen.
When RS-FEC is enabled in the transmit direcon, data to be FEC-encoded and transmied is
provided from the fabric to the input of the GTM transceiver. The pre-FEC data must be pre-
formaed to contain zero padding regions where the parity will be inserted. The Integrated KP4
RS-FEC performs RS encoding to ll in the parity space, and (except in raw mode) also performs
symbol distribuon operaons according to the 802.3bj clause 91 specicaon. The encoded
output data from the Integrated KP4 RS-FEC is then presented to the GTM PCS for transmission.
The Integrated KP4 RS-FEC does not navely perform transcoding, alignment marker removal,
alignment marker mapping, or alignment marker inseron operaons in the transmit direcons.
To support protocols such as 100G Ethernet (IEEE 802.3 clause 91) and 50G Ethernet (IEEE
802.3 clause 134) which require 257b transcoding and alignment marker processing, the GTM
Wizard IP can oponally include so logic blocks for these funcons.
Ports and Attributes
The following table shows the TX FEC-related ports for the GTM dual.
Table 32:
TX FEC Ports
Ports Dir Clock Domain Description
CH[0/1]_TXFECRESET In Async Component reset port for TX FEC.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 63
Send Feedback

Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English