Xilinx Virtex UltraScale+ FPGAs User Manual

Table 32: TX FEC Ports (cont'd)
Ports Dir Clock Domain Description
CH[0/1]_TXDATA[159:0] In CH[0/1]_TXUSRCLK2 Input TX data, must use 160-bit interface
when FEC is enabled.
CH[0/1]_TXDATASTART In CH[0/1]_TXUSRCLK2 Start of codeword.
The transmit poron of the Integrated KP4 RS-FEC operates internally in the CH0_TXUSRCLK
and CH1_TXUSRCLK domains. Data input on CH0_TXDATA is clocked on the rising edge of
CH0_TXUSRCLK2, and data input on CH1_TXDATA is clocked on the rising edge of
CH1_TXUSRCLK2, just as when the FEC is not enabled.
When congured in 100G mode (combined slice 0 and slice 1 operaon), all data from both
channels must be driven by the CH0_TXUSRCLK2 clock. The CH1_TXUSRCLK and
CH1_TXUSRCLK2 inputs can be ed to ground.
The following table shows the TX FEC-related aributes for the GTM dual.
Table 33: TX FEC Attributes
Attribute Type Description
FEC_CFG0 16-bit Reserved.
Bit Name Address Description
FEC_TX0_MODE [3:0] Operation mode for FEC TX slice 0:
4’b0000: FEC is disabled for this channel.
4’b0001: 50G KP4 FEC, 50GAUI-1 format.
4’b0010: 100G KP4 FEC, 100GAUI-2 format.
4’b0101: 50G raw KP4 FEC without scrambling.
4’b1101: 50G raw KP4 FEC with scrambling.
Others: Invalid.
FEC_TX1_MODE
[7:4] Operation mode for FEC TX slice 1:
4’b0000: FEC is disabled for this channel.
4’b0001: 50G KP4 FEC, 50GAUI-1 format.
4’b0010: 100G KP4 FEC, 100GAUI-2 format.
4’b0101: 50G raw KP4 FEC without scrambling.
4’b1101: 50G raw KP4 FEC with scrambling.
Others: Invalid.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 64
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English