Xilinx Virtex UltraScale+ FPGAs User Manual

Ports and Attributes
The following table denes the aributes required for RX Gray Encoder control.
Table 58: Gray Encoder Attributes
Attribute Type Description
CH[0/1]_RX_PCS_CFG0 16-bit Reserved.
Bit Name Address Description
RX_GRAY_ENDIAN [13] In PAM4 mode, this attribute controls the received
endianness. In NRZ mode, the default Wizard value
must be used.
1’b0: Non-inverting.
1’b1: Inverting.
RX_GRAY_BYP_EN
[12] In PAM4 mode, this attribute enables Gray
encoding. In NRZ mode, the default Wizard value
must be used.
1’b0: Enables Gray encoding.
1’b1: Disables Gray encoding.
IMPORTANT! In PAM4 mode, if the Gray Encoder is enabled for the receiver, the transmier Gray
Encoder should also be enabled for proper data recovery.
RX Polarity Control
If the RXP and RXN dierenal traces are accidentally swapped on the PCB, the dierenal data
received by the GTM RX is reversed. The GTM RX allows inversion to be done on parallel bytes
in the PCS aer the SIPO to oset reversed polarity on the dierenal pair. The polarity control
funcon uses the CH0_RXPOLARITY and CH1_RXPOLARITY input, which is driven High from
the interconnect logic interface to invert polarity.
Ports and Attributes
The following table denes the ports required for RX polarity control.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 100
Send Feedback

Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English