Kintex
®
UltraScale™ devices provide the best price/performance/wa at 20 nm and include the
highest signal processing bandwidth in a mid-range device, next-generaon transceivers, and
low-cost packaging for an opmum blend of capability and cost-eecveness. The family is ideal
for packet processing in 100G networking and data centers applicaons as well as DSP-intensive
processing needed in next-generaon medical imaging, 8k4k video, and heterogeneous wireless
infrastructure.
Zynq
®
UltraScale+™ MPSoC devices provide 64-bit processor scalability while combining real-
me control with so and hard engines for graphics, video, waveform, and packet processing.
Integrang an ARM
®
-based system for advanced analycs and on-chip programmable logic for
task acceleraon creates unlimited possibilies for applicaons including 5G Wireless, next
generaon ADAS, and Industrial Internet-of-Things.
This user guide describes the UltraScale architecture GTM transceivers and is part of the
UltraScale architecture documentaon suite available at: www.xilinx.com/ultrascale.
Features
The GTM transceiver in the UltraScale+ FPGA is a high performance transceiver, supporng line
rates between 9.8 Gb/s and 58 Gb/s. Based on the available PLL divider conguraons in the
GTM transceivers, the following line rates are supported:
• PAM4 modulaon:
○ 58 Gb/s – 39.2 Gb/s
○ 29 Gb/s – 19.6 Gb/s
• NRZ modulaon:
○ 29 Gb/s – 19.6 Gb/s
○ 14.5 Gb/s – 9.8 Gb/s
The GTM transceiver is Xilinx’s rst PAM4 enabled transceiver that is highly congurable and
ghtly integrated with the programmable logic resources of the FPGA. The table below
summarizes the features by funconal group that support a wide variety of applicaons.
Table 1: GTM Transceiver Features
Group Feature
PCS
KP4 Reed-Solomon forward error correction (RS-FEC) for up to 2 x 58 Gb/s or 1 x 116 electrical and optical links
PRBS generator and checker
Programmable FPGA logic interface
Chapter 1: Transceiver and Tool Overview
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 6