Xilinx Virtex UltraScale+ FPGAs

Table 1: GTM Transceiver Features (cont'd)
Group Feature
PMA
LC tank oscillator PLL (LCPLL) for best jitter performance
Flexible clocking with one PLL per Dual (two channels)
Programmable TX output
TX FIR filter with de-emphasis controls
Continuous time linear equalizer (CTLE)
Decision feedback equalization (DFE)
Feed forward equalization (FFE)
Notes:
1. A dual is a cluster or set of two GTM transceiver channels. One GTM_DUAL primitive, one differential reference clock
pin pair, and analog supply pins. There is no channel primitive.
The GTM transceiver supports NRZ and PAM4
modulaon as well as the following protocols:
• 100GE CAUI2
• 100GE CAUI4
• 200GE CCAUI4
• 400GE (CDAUI8)
• 50GE LAUI
• 50GE LAUI2
• Ethernet AN/LT (auto negoaon/link training)
• OTU4
• Interlaken at 53.125 Gb/s, 25.78125 Gb/s, and 12.5 Gb/s
• CPRI at 48 Gb/s, 24 Gb/s, 12 Gb/s, and 10.1 Gb/s
The rst-me user is recommended to read High-Speed Serial I/O Made Simple, which discusses
high-speed serial transceiver technology and its applicaons. The Xilinx Vivado
®
IP catalog
includes an UltraScale+ FPGAs GTM Transceivers Wizard to automacally congure GTM
transceivers to support conguraons for dierent protocols and perform custom conguraons.
The GTM transceiver oers a data rate range and features that allow physical layer support for
various protocols. The following gure illustrates the clustering of one GTM_DUAL primive.
Chapter 1: Transceiver and Tool Overview
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 7
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