Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 1: GTM Dual Configuration
LCPLL
GTM_DUAL
REFCLK
Distribution
IBUFDS_GTM /
OBUFDS_GTM
GTM Channel 0 (CH0)
RX
TX
GTM Channel 1 (CH1)
RX
TX
X20210-061418
The GTM_DUAL primive contains one LCPLL and two GTM channels. Contrary to other
UltraScale+ device transceivers such as the GTH and GTY transceivers, the GTM transceiver
does not contain channel/common primives. All channel ports and aributes are within the
GTM_DUAL primive. The following gure illustrates the topology of a GTM channel.
Chapter 1: Transceiver and Tool Overview
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 8
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English