Xilinx Virtex UltraScale+ FPGAs User Manual

TX PRBS paern generator is disabled and the TX is driven based on the CH[0/1]_TXDATA
input.
TX Polarity Control
If TXP and TXN dierenal traces are accidentally swapped on the PCB, the dierenal data
transmied by the GTM transceiver TX is reversed. One soluon is to invert the parallel data
before serializaon and transmission to oset the reversed polarity on the dierenal pair. The
TX polarity control can be accessed through the CH0_TXPOLARITY and CH1_TXPOLARITY
input from the interconnect logic interface. The TX polarity control is driven High to invert the
polarity of outgoing data.
Ports and Attributes
The following table denes the ports required for TX polarity control.
Table 40: TX Polarity Control Ports
Port Dir Clock Domain Description
CH0_TXPOLARITY
1
In CH0_TXUSRCLK2 The CH0_TXPOLARITY port is used to invert the
polarity of the outgoing data for channel 0:
0: Not inverted. TXP is positive, and TXN is
negative.
1: Inverted. TXP is negative, and TXN is
positive.
CH1_TXPOLARITY
1
In CH1_TXUSRCLK2 The CH1_TXPOLARITY port is used to invert the
polarity of the outgoing data for channel 1:
0: Not inverted. TXP is positive, and TXN is
negative.
1: Inverted. TXP is negative, and TXN is
positive.
Notes:
1. CH[0/1]_TXPOLARITY can be tied High if the polarity of TXP and TXN needs to be reversed.
TX Gray Encoder
GTM transmiers in UltraScale+ devices support two types of binary encoding opons: linear
coding and Gray coding. By using Gray coding, only one bit error per symbol is made for incorrect
decisions, thus reducing the bit-error rate by more than 33%. The following gure illustrates the
dierences between linear coding and Gray coding.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 71
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English