Xilinx Virtex UltraScale+ FPGAs User Manual

Usage Model
When FEC is enabled in 50G mode, bit 0 of each TXDATA bus must be the rst bit to be
transmied in me, and bit 159 must be the last bit to be transmied in me. The
TXDATASTART signal must be driven High whenever the TXDATA for the associated channel
contains the rst 160 bits of a codeword. Input codewords must always be aligned so that bit 0
of a codeword is on bit 0 of the TXDATA bus.
When FEC is enabled in 100G mode, bit 0 of CH0_TXDATA must be the rst bit to be
transmied in me, and bit 159 of CH1_TXDATA must be the last bit to be transmied in me.
The CH0_TXDATASTART signal must be driven High whenever the TXDATA buses contain the
rst 320 bits of a codeword. Input codewords must always be aligned so that bit 0 of a codeword
is on bit 0 of CH0_TXDATA. CH1_TXDATASTART is ignored in 100G mode.
In all modes, codewords are 5440 bits in length. The nal 300 bits of data is reserved for the
inseron of FEC parity. At the input to the FEC, bits 5140 to 5439 of the input data must be set
to 0.
50G Ethernet
Up to two channels of 50G Ethernet with KP4 FEC can be implemented as per IEEE Dra
Standard for Ethernet Amendment: Media Access Control Parameters for 50 Gb/s and Physical Layers
and Management Parameters for 50 Gb/s, 100 Gb/s, and 200 Gb/s Operaon (IEEE Std 802.3cd
Clause 134). Transcoding should be enabled in the GTM Wizard IP for this mode. The nominal
pre-FEC PCS data rate is 51.5625 Gb/s, and the nominal post-FEC line rate is 53.125 Gb/s.
100G Ethernet
One channel of 100G Ethernet with KP4 FEC can be implemented as per IEEE Std 802.3-2015
Clause 91. Transcoding should be enabled in the GTM Wizard IP for this mode. The nominal
aggregate pre-FEC PCS data rate is 103.125 Gb/s and the nominal aggregate post-FEC line rate
is 106.25 Gb/s.
100G OTN FlexO
One channel of 100G OTN FlexO with a KP4 FEC can be implemented as per ITU-T G.709.1,
Flexible OTN Short-Reach Interface. Transcoding should be disabled in the GTM Wizard IP for this
mode. The nominal aggregate post-FEC line rate is 111.81 Gb/s.
100G Interlaken
One channel of 100G Interlaken with KP4 FEC can be implemented as per the Interlaken Reed-
Solomon Forward Error Correcon Extension Protocol Denion. Transcoding should be disabled in
the GTM Wizard IP for this mode. Line rates up to 58 Gb/s are possible.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 65
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English