Xilinx Virtex UltraScale+ FPGAs - Page 4

RX CDR........................................................................................................................................ 93
RX Fabric Clock Output Control............................................................................................... 94
RX Margin Analysis....................................................................................................................98
RX Pre-Coder..............................................................................................................................99
RX Gray Encoder........................................................................................................................99
RX Polarity Control.................................................................................................................. 100
RX Pattern Checker................................................................................................................. 101
RX Buffer...................................................................................................................................104
RX FEC....................................................................................................................................... 106
RX Interface..............................................................................................................................113
Chapter 5: Board Design Guidelines................................................................ 117
Pin Description and Design Guidelines................................................................................ 117
Reference Clock....................................................................................................................... 120
GTM Transceiver Reference Clock Checklist........................................................................ 122
Reference Clock Interface...................................................................................................... 123
AC Coupled Reference Clock..................................................................................................124
Unused Reference Clocks.......................................................................................................125
Reference Clock Output Buffer..............................................................................................125
Reference Clock Power...........................................................................................................125
Power Supply and Filtering.................................................................................................... 125
PCB Design Checklist.............................................................................................................. 129
Appendix A: DRP Address Map of the GTM Transceiver in
UltraScale+ FGPAs.................................................................................................. 133
GTM_DUAL Primitive DRP Address Map...............................................................................133
Appendix B: Additional Resources and Legal Notices........................... 143
Xilinx Resources.......................................................................................................................143
Documentation Navigator and Design Hubs...................................................................... 143
Please Read: Important Legal Notices................................................................................. 144
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 4
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