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ZiLOG Z8 Series User Manual
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Z8
®
CPU
User Manual
UM001604-0108
External Interface
135
clock is shown for clarity only and
does not ha
ve a specific timing relationship with other
signals.
Figure 126. External
Instruction Fetch or Memory Read Cycle
Machine Cycle
T1
T2*
T3
Clock
A15-A8
AD7–AD0
AS
DS
R/W
DM
Read Cycle
A8-A15
A7–A0
D7–D0 IN
*Port inputs are stro
bed during T
2, which is two intern
al systems clocks
before the execution
cycle of the current instruction.
141
143
Table of Contents
Default Chapter
4
Table of Contents
4
Z8 ® CPU Product Overview
8
Key Features
8
Product Development Support
10
Address Space
12
Introduction
12
Z8 ® CPU Standard Register File
12
General-Purpose Registers
14
RAM Protect
14
Working Register Groups
14
Error Conditions
17
Z8 Expanded Register File
17
Z8 ® Control and Peripheral Registers
22
Standard Z8 Registers
22
Expanded Z8 Registers
23
Program Memory
26
Z8 ® External Memory
27
External Data Memory
28
Z8 ® Stacks
29
Clock
31
Frequency Control
31
Clock Control
31
SCLK ÷ TCLK Divide-By-16 Select
32
External Clock Divide-By-Two
32
Oscillator Control
33
Oscillator Operation
34
Layout
35
Indications of an Unreliable Design
35
Circuit Board Design Rules
35
Crystals and Resonators
36
LC Oscillator
38
RC Oscillator
39
Reset
40
Reset Pin, Internal por Operation
40
Watchdog Timer
47
Power-On Reset
49
Input/Output Ports
50
Mode Registers
50
Input and Output Registers
51
Port 0
51
General I/O Mode
52
Read/Write Operations
54
Handshake Operation
54
Port 1
55
General I/O Mode
55
Read/Write Operations
57
Handshake Operations
58
Port 2
59
General Port I/O
59
Read/Write Operations
61
Handshake Operation
62
Port 3
63
General Port I/O
63
Read/Write Operations
68
Special Functions
68
Port Handshake
70
I/O Port Reset Conditions
73
Full Reset
73
Analog Comparators
75
Comparator Description
75
Comparator Programming
78
Comparator Operation
79
Interrupts
79
Comparator Definitions
79
Run Mode
80
Halt Mode
80
Stop Mode
80
Open-Drain Configuration
80
Low EMI Emission
81
Input Protection
82
Z8 ® CMOS Autolatches
84
Autolatch Model
85
Design Considerations
85
Counters and Timers
87
Prescalers and Counter/Timers
88
Counter/Timer Operation
90
Load and Enable Count Bits
90
Prescaler Operations
91
TOUT Modes
93
TIN Modes
95
External Clock Input Mode
96
Gated Internal Clock Mode
97
Triggered Input Mode
97
Retriggerable Input Mode
98
Cascading Counter/Timers
98
Reset Conditions
99
Interrupts
102
Interrupt Sources
103
External Interrupt Sources
104
Internal Interrupt Sources
105
Interrupt Request Register Logic and Timing
105
Interrupt Initialization
106
Interrupt Priority Register Initialization
107
Interrupt Mask Register Initialization
108
Interrupt Request Register Initialization
109
IRQ Software Interrupt Generation
111
Vectored Processing
112
Vectored Interrupt Cycle Timing
114
Nesting of Vectored Interrupts
115
Polled Processing
115
Reset Conditions
116
Power-Down Modes
117
Halt Mode Operation
117
Stop Mode Operation
117
Stop Mode Recovery Register
119
Serial Input/Output
122
UART Introduction
122
UART Bit-Rate Generation
123
UART Receiver Operation
125
Receiver Shift Register
125
Overwrites
126
Framing Errors
126
Parity
126
Transmitter Operation
127
Overwrites
128
Parity
128
UART Reset Conditions
129
Serial Peripheral Interface
129
SPI Operation
132
SPI Compare
132
SPI Clock
132
Receive Character Available and Overrun
133
External Interface
138
Introduction
138
Pin Descriptions
138
External Addressing Configuration
139
External Stacks
140
Data Memory
141
Bus Operation
141
Address Strobe
143
Data Strobe
143
Extended Bus Timing
144
Instruction Timing
145
Z8 ® Reset Conditions
147
Instruction Set
148
Processor Flags
151
Carry Flag
151
Zero Flag
152
Sign Flag
152
Overflow Flag
152
Decimal Adjust Flag
152
Half Carry Flag
153
Condition Codes
153
Notation and Binary Encoding
154
Assembly Language Syntax
156
Z8 ® Instruction Summary
157
Op Code Map
163
Instruction Description
164
Index
257
Customer Support
260
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ZiLOG Z8 Series Specifications
General
Brand
ZiLOG
Model
Z8 Series
Category
Microcontrollers
Language
English
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