Z8
®
CPU
User Manual
UM001604-0108 Address Space
15
Refer to the specific product specification to determine the above registers are imple-
mented.
Z8
®
Control and Peripheral Registers
Standard Z8 Registers
The standard Z8 control registers govern the operation of the CPU. Any instruction which
references the register file can access these control registers. The following control regis-
ters are available:
•
Interrupt Priority Register (IPR)
•
Interrupt Mask Register (IMR)
•
Interrupt Request Register (IRQ)
Table 7. Z8 ERF Bank Layout
ERF Bank ERF
Fh PCON, SMR, WDT, (00h, 0Bh, 0Fh), Working Register Group 0 only
implemented.
Eh Not implemented (reserved)
Dh Not implemented (reserved)
Ch SPI Registers: SCOMP, RXBUF, SCON (00h, 01h, 02h), Working
Register Group 0 only implemented.
Bh Not implemented (reserved)
Ah Not implemented (reserved)
9h Not implemented (reserved)
8h Not implemented (reserved)
7h Not implemented (reserved)
6h Not implemented (reserved)
5h Not implemented (reserved)
4h Not implemented (reserved)
3h Not implemented (reserved)
2h Not implemented (reserved)
1h Not implemented (reserved)
0h Z8 Ports 0, 1, 2, 3, and General-Purpose Registers 04h to EFh, and
control registers F0h to FFh.
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