Z8
®
CPU
User Manual
UM001604-0108 Interrupts
102
The RAM Protect option is selected at ROM mask submission time or at EPROM program
time. If not selected or not an available option, this bit is reserved and must be 0.
Interrupt Request Register Initialization
The Interrupt Request Register (IRQ), displayed in Figure 98 on page 103, is a read/write
register that stores the interrupt requests for both vectored and polled interrupts. When an
interrupt is made on any of the six, the corresponding bit position in the register is set to 1.
Bit 0 to bit 5 are assigned to interrupt requests IRQ0 to IRQ5, respectively.
Whenever Power-On Reset (POR) is executed, the IRQ resister is reset to
00h and dis-
abled. Before the IRQ register accepts requests, it must be enabled by executing an
ENABLE INTERRUPTS (EI) instruction.
Setting the Global Interrupt Enable bit in the Interrupt Mask Register (IMR, bit 7) does not
enable the IRQ. Execution of the EI instruction is required (see Figure 99 on page 104).
For polled processing, IRQ must still be initialized by an EI instruction. To properly ini-
tialize the IRQ register, the following code is provided.
Figure 97. Interrupt Mask Register
CLR IMR // Make sure vectored interrupts are disabled.
D7 D6 D5 D4 D3 D2 D1 D0
(Read/Write)
Interrupt Request Register (IMR)
Register FBh
0 = Disables IRQ0
1 = Enables IRQ0
0 = Disables IRQ1
1 = Enables IRQ1
0 = Disables IRQ2
1 = Enables IRQ2
0 = Disables IRQ3
1 = Enables IRQ3
0 = Disables IRQ4
1 = Enables IRQ4
0 = Disables IRQ5
1 = Enables IRQ5
0 = Disables RAM Protect
1 = Enables RAM Protect
0 = Disables Interrupt
1 = Enables Interrupt
Note:
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