Z8
®
CPU
User Manual
UM001604-0108 Clock
25
SCLK ÷ TCLK Divide-By-16 Select
The D0 bit of the SMR controls a divide-by-16 prescaler of SCLK ÷ TCLK. The purpose
of this control is to selectively reduce device power consumption during normal processor
execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and
interrupt logic).
External Clock Divide-By-Two
The D1 bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, SCLK
(System Clock) and TCLK (Timer Clock) are equal to the external clock frequency
divided by two. The SCLK ÷ TCLK is equal to the external clock frequency when this bit
is set (D1 = 1). Using this bit, together with D7 of PCON, further helps lower EMI (D7
(PCON) = 0, D1 (SMR) = 1). The default setting is 0. Maximum frequency is 4 MHz with
D1 = 1 (see Figure 14 on page 26).
Figure 13. Stop Mode Recovery Register (Write-Only Except D7, Which is Read-Only)
D7 D6 D5 D4 D3 D2 D1 D0
SMR (F) OB
SCLK ÷ TCLK Divide by 16
0 OFF **
1 ON
External Clock Divide Mode by 2
0 = SCLK ÷ TCLK = XTAL ÷ 2*
1 = SCLK ÷ TCLK = XTAL
* Default setting after RESET.
**Default setting after RESET and Stop Mode Recovery.
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