ZiLOG Z8 Series

Z8
®
CPU
User Manual
UM001604-0108 Counters and Timers
92
Reset Conditions
After a hardware reset, the counter/timers are disabled and the contents of the counter/
timer and prescaler registers are undefined. However, the counting modes are configured
for Single-Pass and the T1 clock source is set for external.
T
IN
is set for External Clock mode, and the T
OUT
mode is OFF. Figure 87 on page 93
through Figure 89 on page 94 displays the binary reset values of the Prescaler, Counter/
Timer, and Timer Mode registers.
Figure 85. Cascaded Counter/Timers
Figure 86. Counter/Timer Reset
OSC
÷ 2 ÷ 4
PRE0 T0
÷ 2PRE1
IRQ
2
P3
1
P3
6
T1
IRQ
4
T
OUT
T
IN
IRQ
5
U U U U U U U U
(%F4; Write/Read Only)
current value when read
Initial value when written
(Range 1–256 decimal, 01–00 HEX)
Counter/Timer 0 Register
R244 T0
(%F2; Write/Read Only)
Counter/Timer 1 Register
R242 T1