ZiLOG Z8 Series User Manual

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
178
Decrement Word
Syntax
DECW dst
Instruction Format
Operation
dst ← dst–1
The contents of the destination (which must be an even address) operand are decremented
by one. The destination operand can be a Register Pair or a Working Register Pair.
Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this for-
mat, the destination Working Register Pair operand is specified by adding
1110b (Eh) to
the high nibble of the operand. For example, if Working Register Pair R12 (CH) is the des-
tination operand, then
ECh is used as the destination operand in the Op Code.
Example 1
If Register Pair 30h and 31h contain the value 0AF2h, the statement:
DECW 30h
Op Code: 80 30
leaves the value 0AF1h in Register Pair 30h and 31h. The Z, V, and S Flags are cleared.
Example 2
If Working Register R0 contains 30h and Register Pairs 30h and 31h contain the value
FAF3h, the statement:
Cycles
OPC
(Hex)
Address Mode
dst
OPC dst
10 80 RR
10 81 IR
Flag Description
C Unaffected
Z Set if the result is zero; cleared otherwise
S Set if the result of bit 7 is set (negative); cleared otherwise
V Set if arithmetic overflow occurs; cleared otherwise
D Unaffected
H Unaffected
Edst
Note:

ZiLOG Z8 Series Specifications

General

Brand	ZiLOG
Model	Z8 Series
Category	Microcontrollers
Language	English