Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
197
Load Constant Autoincrement
Syntax
LDCI dst, src
Instruction Format
Operation
dst ← src
r ← r + 1
rr ← rr + 1
This instruction is used for block transfers of data between Program Memory and the Reg-
ister File. The address of the Program Memory location is specified by a Working Register
Pair, and the address of the Register File location is specified by Working Register. The
contents of the source location are loaded into the destination location. Both addresses in
the Working Registers are then incremented automatically. The contents of the source
operand are not affected.
Example 1
If Working Register Pair R6–R7 contains 30A2h, Program Memory location 30A2h and
30A3h contain 22h and BCh respectively, and Working Register R2 contains 20h, the
statement:
LDCI @R2, @RR6
Op Code: C3 26
loads the value 22h into Register 20h. Working Register Pair RR6 is incremented to
30A3h and Working Register R2 is incremented to 21h. A second
Cycles
OPC
(Hex)
Address Mode
dst src
OPC dst src 18 C3 Ir Irr
OPC dst src 18 D3 Irr Ir
Flag Description
C Unaffected
Z Unaffected
S Unaffected
V Unaffected
D Unaffected
H Unaffected
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