ZiLOG Z8 Series User Manual

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
228
Set Register Pointer
Syntax
SRP src
Instruction Format
Operation
RP ← src
The specified value is loaded into the Register Pointer (RP) (Control Register FDh). Bits
7-4 determine the Working Register Group. Bits 3-0 selects the Expanded Register Bank.
Addressing of un-implemented Working Register Group, while using Expanded Register
Banks, points to Bank 0.
Example 1
SRP TD addresses Working Register Group 7 of Bank 0.
Cycles
OPC
(Hex)
Address Mode
dst
OPC src 6 31 IM
Register Pointer
(FDh)
Working Register
Group Actual Registers
Contents (Bin) (Hex) (Hex)
1111 0000 F F0–FF
1110 0000 E E0–EF
1101 0000 D D0–DF
1100 0000 C C0–CF
1011 0000 B B0–BF
1010 0000 A A0–AF
1001 0000 9 90–9F
1000 0000 8 80–8F
0111 0000 7 70–7F
0110 0000 6 60–6F
0101 0000 5 50–5F
0100 0000 4 40–4F
0011 0000 3 30–3F
0010 0000 2 20–2F
0001 0000 1 10–1F
0000 0000 0 00–0F

ZiLOG Z8 Series Specifications

General

Brand	ZiLOG
Model	Z8 Series
Category	Microcontrollers
Language	English