ZiLOG Z8 Series

Z8
®
CPU
User Manual
UM001604-0108 Input/Output Ports
57
Figure 44. Port 3 Block Diagram
Input
Buffer
Input
Register
Output
Buffer
Output
Register
Output
Register
Write
Port
Read
Port
4
4
4
4
4
4
4
4
Internal
Bus
From Timer,
Handshake Logic,
or Serial I/O
To Interrupt Timer,
Handshake Logic,
or Serial I/O
Port
Output
Lines
P3
4
–P3
7
Port
Input
Lines
P3
0
–P3
3
Read
Port
Input
Buffer
Output
Buffer
Output
Register
Output
Buffer
Data
Return