ACT apricot - Page 144

SERIAL INTERFACE
Write Register o.
I D71 D61 D51 D41 D31 D21 D 1 I DO I WRO
Pointers
0 0 0 Register 0
0 0
1 Register 1
0
1
0 Register 2
0
1 1 Register 3
1
0
0
Register 4
1
0
1
Register 5
1
1
0
Register 6
1 1 1
Register 7
Command Operation
0 0
0
Null code
0 0 1 SDLC Send Abort
0
1
0
Reset Ext/Status Interrupts
0
1
1
Channel Reset
1
0
0
Reset Rx Int. on 1st character
1
0 1
Reset
Tx Int. pending
1 1
0
Error reset
1 1
1
Return from Interrupt
(Ch.A only)
Auxiliary Resets
o 0 Null code
o 1 Reset Rx CRC checker
1
0 Reset Tx CRC generator
1 1 Reset Transmit Underrun/EOM latch
Pointers (DO to D2). These bits signify the register for the
next command/status transfer operation. If the next
operation is a write, the pointer specifies a write register. If
the next operation is a read, the pointer specifies a read
register. Following a read or
write to any register (except
WRO), the pointer points to register 0 (i.e. Write Register 0
or Read Register 0).
Commands (D3 to D5). These bits specify eight different
commands,
the function of which are detailed below.
1. Null Code. This command enables the programmer
to specify the next register for a command/status
transfer using the pointer bits, without affecting the
operation of the SIO.