ACT apricot - Page 145

SERIAL INTERFACE
2. SDLC Send Abort. Used only in the bit oriented
synchronous modes. The command causes the SIO to
generate an abort sequence which informs the receiver
of
data from the SIO to terminate reception.
3. Reset Ext/Status Interrupts. After an External
interrupt (caused by a change of state on a modem
control input), or a Status interrupt (caused by
detecting a break/abort/ condition in receive data or a
transmit underrun/EOM condition in transmit data),
corresponding status bits within Read Register 0 are
latched. This command re-enables the bits and allows
further interrupts to occur.
4.
Channel Reset. This command performs the same
function as a hardware reset but on the specified
channel only. Issuing the command to channel A also
resets the interrupt logic, clearing any current and all
pending interrupts. All Write Registers in the channel
must be reprogrammed, following the command.
5. Reset Rx Interrupt on First Character. If the
Interrupt on First Receive Character Mode is in
operation (bits 3 and 4 of WRl), an interrupt is
generated on receiving the first character. At the end of
the message, this command is issued to reactivate the
mode.
6. Reset Tx Interrupt Pending. If the Transmit
Interrupt is enabled (bit 1 of WRl), the SIO generates
an interrupt every time the transmit buffer is empty.
Issuing the Reset Tx Interrupt Pending command,
resets the transmit interrupt, and prevents the
interrupt being raised again until the transmit buffer is
loaded with a character and becomes empty again.
7. Error Reset. Parity and Overrun errors are latched
into Read Register 1 (the status register at the top of
the receive error FIFO stack). These error conditions
remain within the register until the Error Reset
Command is issued.