ACT apricot - Page 149

SERIAL INTERFACE
3. Interrupt on all Rx Characters, parity affects vector.
Enables
an interrupt to be generated on detecting:
(a) Any receive character within the receive
buffer.
(b) Any special receive condition.
4, Interrupt on all Rx Characters, parity does not affect
vector. Enables
an interrupt to be generated on detecting:
(a) Any receive character within the receive
buffer.
(b) Any special receive condition apart from a
Parity error.
Ready Controls {D5 to D7}. These three bits control the
state of the W/RDYA output of channel A, which is
connected to the DMArequest line DRQ2 of the Input
Output Processor (lOP). A W IRDYB output is not provided
on a Z80 SIOIO, so these bits are redundant in channel B.
The function of the three bits are as detailed below.
1. Ready On Rx/Tx (DS). With the Ready Function and
Ready Enable bits set to logic high, the condition for
generating a DMA request is dependent on the state of
the Ready On Rx/Tx bit, as follows:
(a) When programmed to logic low, the DMA
request line is set and reset according to whether
the transmit buffer is empty or full. Every time
the transmit buffer is empty, the SIO sets WI
RDYA to logic low, which signifies to the lOP
that transmit data is required. Every time the lOP
responds by writing a new byte of data in to the
transmit buffer, the SIO resets the W/RDYA
output to logic high.
(b) When programmed to logic high, the DMA
request line is set and reset according to whether
the receive buffer is empty or full. Every time the
receive buffer is full, the SIO sets W IRDYA to
logic low, which signifies to the lOP that receive
data is available. Every time the lOP responds by
reading the byte of data, the SIO resets the
W/RDYA output to logic high.