ACT apricot - Page 151

SERIAL INTERFACE
Write Register 3
I D71 DSI D5l D4 I D31 D21 D 1 I DO I WRJ
~
I LRX Enable
~sync Char Load Inhibit
Address search mode (SDLC)
~Rx eRC Enable
~Enter Hunt mode
Auto Enables
o 0 5 bits/character
lOS bits/character
o 1 7 bits/character
1 1 8 bits/character
Rx Enable (DO). If set to logic high, the receiver circuits are
enabled
to accept data from the serial link. If set to logic
low,
the receiver circuits are disabled.
Sync Character Load Inhibit (Dl). Setting this bit to logic
high prevents any sync characters being loaded into the
receive FIFO stack.
Address Search Mode (D2). If a bit oriented synchronous
mode is selected and this bit is set to logic high, only
messages
with an address (following the opening flag)
matching either the programmed address in Write Register
6 or
the global address (FFH), are accepted by the receiver
circuits.
If set to logic low, no address searchls carried out.
Rx CRC Enable (D3). This bit enables (logic high)/disables
(logic low)
the receiver eRC error detection circuits.
Enter Hunt Mode {D4}. The Hunt mode in synchronous
modes is automatically entered following a reset. If
character synchronisation is lost (any Sync mode) or the
incoming data is not required (SDLC), the hunt phase can be
re-entered by
setting D4 to logic high.