ACT apricot - Page 152

SERIAL INTERFACE
Auto Enables (D5). Setting this bit to logic high allows the
two modem input control lines, DCD and CTS to control
data transfers over the serial data link. DCD controls the
SIO receiver circuits, CTS the transmitter circuits.
Rx bits/character (D6, D7). The combination of these two
bits determine the number of receive bits assembled to form
a character.
Write Register 4
1
07
1
06
1
05
1
04
1
03
1
02
1 01 1
00
1 WR4
~ ~paritY Enable
Parity Even/odd
Mode Select
o 0 Enable Sync Mode
o 1 1 stop bit/character
1 0 1.5 stop bits/character
1 1 2 stop bits/character ~
Sync Mode
o 0 Monosync
o 1 Bisync
1 0 SOLC/HOLC
1 l( External sync
o 0 xl clock rate
o 1 x16 clock rate
1 0 x32 clock rate
1 1 x64 clock rate
Parity Enable (DO). If this bit is set to logic high, a parity bit
is added to the transmit character data and is expected in
receive data.
Parity Even/Odd (DI). This bit is used when the Parity
Enable bit is set to logic high to determine the sense of the
parity code in the transmit data and the expected parity
code in receive data. Even parity is signified by setting this
bit to logic high, odd parity by setting the bit to logic low.