ACT apricot - Page 153

SERIAL INTERFACE
Mode Select (D2, D3). The combination of these two bits
differen
tia te between asynchronous and synchronous
modes of operation
and also specify the number of stop bits
added
to the transmit data in the asynchronous mode. The
receiver circuits always check for one stop bit in the receive
data, regardless of
the number of stop bits in the transmit
data.
Sync Mode (D4, D5). If synchronous mode is selected by the
Mode Select bits, these bits determine the type of
synchronous mode, for
transmit and receive data.
Clock Rate (D6, D7). These bits specify the multiplier
applied to both the transmit and receiver input clock rate
prior to being
used to set the transmit and receive baud
rates. For
synchronous modes the xl clock rate must be
selected.
Any rate may be selected for the asynchronous
mode, apart from
the xl rate.
Write Register 5
1 D71 D61 D51 D41 D31 D21 Dl 1 DO 1 WR5
I I I RTS Tx CRC Enable
LCRC~16
'----- Tx Enable
""'----- Send Break
Tx bits/character
o 0 5 bits/character or less
1 0 6 bits/character
o 1 7 bits/character
1 1 8 bits/character
-DTR
Tx CRC Enable (DO). This bit enables (logichigh)/disables
(logic low)
the CRC generator in the transmit data path.