ACT apricot - Page 180

PARALLEL INTERFACE
-------'..ID?
PERIPHERALS DATA BUS TO
-------,11 DO
SYSTEM CONTROL BUS (IDRC.AIDWC) Rll,lJR
PID
PCI (I----t------i
DISPLAY ENABLE (DE)
fROM CRT CONTROL
TRANSCEIVER
BUffER
CENTRONICS
CONNECTOR
8-BIT DATA
~)ALL~g! TED
DATA STROBE
fAULT
cs 8255A-5 pcc
SELECT
PE
ACK
BUSY
A2
Al
Al
AD
SYSTEM RESET fROM
CLOCK GENERATOR
RES
PB?
~:~ t------+) D~~~p~~L~~~K L~~~0E~O
VIA A DECODER
PB4t-----,
PB3 A/G SELECT TO CRT CONTROL
~!~ DISPLAY ON <DllN) TO VIDEO INTERfACE
HLD TO fLOPPY DISK DRIVES
VIA AN INVERTER
RrsrT TO CRT CONTROL
c-~l~L,
,"S'i'fIC1fC1nllm,
Z80 SID
Figure I.Parallel Interface block diagram
PIO Pin Definition
PAOto PA7
PBO toPB7
PCOtoPC7
DOtoD7
RD
WR
CS
AO/AI
Port A,
Port B
Port C
Data bus connection
Read
control line
Write control line
Chip select input
System address bus inputs