ACT apricot - Page 181

PARALLEL INTERFACE
DESCRIPTION
General
The Parallel Interface consists of; a programmable
parallel
input output port, an octal bus transceiver, an octal
buffer
and a Centronics connector. The buffer forms the
interface for control signals between the board and the
printer, and the transceiver forms the interface for data from
the board to the printer.
The transceiver (see Figure 1) is bi-directional, with the
direction of data flow controlled by the BIOS. Whilst used as
a
printer port, the flow of data is always in one direction
- only, out to the printer. However with the direction
capability of
the transceiver, the port can be more generally
used for transferring data to and from the Apricot.
The three input control signals, Fault, Ack and Busy are
connected,
via the buffer, to input lines of the serial
interface
on the board (SIO). The three inputs are used to
generate an interrupt to the CPU, utilising the interrupt
capabilities of the SIO.
The Intel 8255A-5 Parallel Input Output Port (PIO) is
organized
internally as three input/output ports, with an
associated control register. The control register determines
the direction and mode of operation of each port.
The system software views the three ports and the control
register as
an array of peripheral ports, with the port address
locations defined by the PIO select and system address bus
connections, as detailed below.
Peripheral Port Address
Data
Port A
48H Printer data
Port B
4AH
System control outputs
Port C
4CH
Printer control inputs/outputs
plus a system control input.
Control register 4EH Control word