ACT apricot - Page 57

INTERRUPT CONTROLLER
modified using anyone of three Operational Control Words
(OCWl, OCW2 or OCW3). The OCWs are not dependent on
each other and can be issued at any time during program
execution.
OCWl provides the facility for enabling/disabling
individual interrupt request lines. This is achieved by
issuing the control word to the 8-bit Interrupt Mask
Register (IMR) within the PIC. The address location of the
IMR is 02H within the system input/output space and the
format of OCW 1 is as follows.
I M71 M61 M51 M41 M31 M21 Ml I MO I DeW1
Each bit within the IMR directly corresponds to an
interrupt request line (MO of the IMR affects IRO, Ml of the
IMR affects IRl, M2 affects IR2 etc.).
Interrupt request lines are disabled (masked) when the
corresponding bit within the IMR is set to logic high, and
enabled (not masked), when the corresponding bit is set to
logic low.
The status of the bits within the mask register can also be
read
by the programmer at address location 02H within the
I/O space.
OCW2 is a dual purpose control word, which allows the
priority of the interrupt requests assigned during the
initialization sequence to be altered, and is also used to
inform the PIC that an interrupt service routine is
terminating.
The facilities prilvided by OCW2 for altering the priority
of the interrupt requests are not required, since the actual
hardware IR connections have been made on the basis of the
priority assigned during the initialization routine.
The format of OCW2, used to inform the PIC that the
interrupt service routine is at an end (enabling the PIC to
reset the associated ISR bit within the Interrupt Service