ACT apricot - Page 63

TIMER
condition for loading one byte only into the counter,
automatically sets the other byte to zero count state. The
counter begins decrementing after the full count value has
been loaded.
Two methods are available to read the count values
reached by
the counters, whilst the counters are counting
down. Both methods have no affect on the operation of the
counters. The first method is achieved by reading the data
stored
at the selected counter address location using two
consecutive read operations. The first read operation
returns the least significant byte of the count state and the
second, the most significant byte.
The second method ensures that a stable count state
reading is obtained by utilising the control word to latch the
count state into a storage register associated with each
counter. The count state is then obtained in the same
manner as the first method. (By performing two consecutive
read operations
to access the stored count values at the
counter address location). To latch the count state into the
storage register, the control word is written into the address
location of
the control word register set, with the format as
detailed below.
D7
DO
c= Logic state ·immaterial '
L...- _____ Defines latch operation
L...- ______ Selects counter
Counter 0
For
the output of Counter 0 (OUT 0) to be used as an
interrupt request line to the Interrupt Controller, the
counter must be set to operate in Mode O. When the counter
is initialized, output (OUT 0) is set to logic low. After the
counter is loaded, the counter begins to count down as
illustrated in the timing diagram, Figure 2 below.