ACT apricot - Page 64

TIMER
The count state is decremented on the negative edge of
each
0.25 MHz clock pulse. On reaching zero count state,
the counter output is set to logic high. Thi~ condition
remains static until reset, (either by re-initializing the
counter or by loading a new value into the counter). The
counter continues to decrement after the zero count state is
reached,starting from the maximum count state of the
counter, until reset. ( 2
16
for a binary counter, 10
4
for a BCD
counter).
This feature allows the software to determine the
exact time of the interrupt request by reading the Counter 0
count state and performing a simple calculation.
CKOnnnJL
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WRU
t
COUNT
$T.;1E
DUTO
C:OU~T STATE ~ .
LATCliED fROM I
DATA BUS
N I N-l I
COU~T STATE
LOADED tNT u COUN r lR
JLJlSl
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Figure 2. Mode 0 timing diagram.
Counter 1 and 2
Counter 1 and Counter 2 are set to operate in Mode 3, to
produce a squarewave
output for use by the RS232C serial
interface.
In Mode 3, a true squarewave is only produced by
programming
the counter with an even count state. Under
this condition, the counter remains at logic high for one half
of the count state, and at logic low for the second half. The
counter is decreased by two on the negative edge of each
2M Hz clock pulse as illustrated in the timing diagram,
Figure 3.
When the counter reaches zero count state, the original
count value is reloaded into the counter and the process
repeated.
This produces a squarewave output with a
frequency
equivalent to the input clock frequency (2 MHz)
divided by
the count state, and a 500/0 duty cycle.