ACT apricot - Page 80

CRT CONTROL
Address Register. S-bit register located at 68H in the system
I/O space and can be written to only. Acts as the pointer for
the other control registers. Prior to any data transfer
between the processors and any of the 18 control registers,
the source/destination register has to be defined by
programming the address register with the address pointer.
The pointer for each control register is the binary equivalent
of the decimal "R" number, e.g. Interlace Mode control
register R8 is specified by programming the address register
with08H.
Horizontal Total Register (RO). The contents of this register
determine the line frequency of the HSync output and is
specified
in CCLK periods. The actual number is equivalent
to the total number of character periods in the active scan
line time and the line retrace period minus one (active +
retrace - 1 character periods).
Horizontal Displayed Register (Rl). This register specifies
the number of characters displayed on each scan line.
HSync Position Register (R2). The contents of this register
specify
the position of the horizontal sync pulse relative to
the start of the active scan line period. The value is
programmed in CCLK periods. The effect of increasing the
value in R2 is to shift all characters displayed on the screen
to the left. Decreasing the value shifts the whole character
display to the right.
HSync Width Register (R3). The contents of R3 set the width
of the Hsync pulse in units of the character clock period.
Vertical Total Register (R4). This register with RS define the
frequency of the VSync pulses. R4 is programmed with a
value,
in character row periods (i.e. 16 scan line periods),
just less
than the desired frequency. The fine adjustment to
achieve
the exact VSync frequency is provided by RS. The
actual value of R4 is one less than the desired number of
character
ro,w periods.
Vertical
Total Adjust Register (RS). This register provides
the fine control of the frequency of VSync and is
programmed in scan line periods.