6-23
Connectors
Signal Descriptions for SYSTEM BUS
RP_HOP_INHIBIT Pin 30 Input
This is the rear-panel internal hop inhibit input. It connects to the hop controller. It is
used to inhibit internal hopping. The internal hop sequence address register is still
sequenced, however. This signal should normally be kept TTL high.
This line is active whenever the hop controller’ hop address source is set to Seq.
Requirements Amplitude: TTL levels High drive requirements: 100 µA Low
drive requirements: 2 mA Active level: Low
See Also Screens: RFG/RFA (Hop Control) Specifications Timing
Diagrams
RP_RST_SEQ_
HOP
Pin 11 Input
This is the rear-panel input to reset the internal hop sequence address register. It
connects to the hop controller. This signal is primarily used to reset the internal hop
address register to zero before a hopping sequence reaches the end of the hop
frequency table(s). The signal should normally be kept TTL high.
This signal is always active. To reset the internal hop sequence counter, however, the
reset will only occur on a subsequent RP_SEQ_HOP signal when the hop
controller’s hop address source is set to Seq.
Requirements Amplitude: TTL levels High drive requirement: 100 µA Low
drive requirement: 2 mA Active level: Low
See Also Screens: RFG/RFA (Hop Control) Specifications Timing
Diagrams
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