Allen-Bradley ClutchBrake PLC-5 Series - Write Ladder Logic; Chapter Objectives; Overview of Memory Organization

Chapter 4
Publication 65566.5.1 - October 1996
Write Ladder Logic
To help you write ladder logic to customize the operation of your
clutch/brake control system, we present the following information:
• overview of memory organization for processors A and B
• data files reserved for control system data
• how command bits act on control logic in protected memory
• select from these command bits
• steps to write ladder logic
• programming command bits
• using fault and prompt bits
• exchanging data between processors with the scanner/adapter channel
• programming shorter presets for your internal timers
• programming press-ready-to-start indicators
• programming a brake monitor
• programming a variable-speed top stop
Important: We suggest that you study the entire chapter before you
begin writing your logic.
Your clutch/brake control system has dual PLC-5/x6 processors: one in I/O
chassis A, the other in chassis B. Memory organization is similar in both
processors. Program files PF2 and PF16 are factory programmed and pass-
word protected for “read only”. You will program your clutch/brake
interface in program file PF15, and your machine-related functions such as
for robotics, lubrication, and die change in pre-assigned subroutine files.
We organized processor memory as follows:
Program File Description (Processor in Chassis A) Description (Processor in Chassis B)
PF2 Factoryconfigured Master Control Program
(Locked)
Identical to processor in chassis A
PF3 Used to call subroutines to control auxiliary
press functions, such as automation valve,
die protection, robotics, etc.
Optional but available for application
programming, independent of
processor in chassis A
PF15 Where you program the clutch/brake
interface with machine sequencing to
customize the clutch/brake code in PF16
Similar to processor in chassis A
PF16 Factoryconfigured clutch/brake code
(read, only)
Identical to processor in chassis A
Other
Subroutines
Preassigned subroutines that you write for
application programming (as needed).
You call these subroutines from PF3.
Available for application programming,
independent of processor A
Chapter Objectives
Overview of
Memory Organization