Allen-Bradley ClutchBrake PLC-5 Series - Programming Shorter Presets for Your Internal Timers

4–20 Write Ladder Logic
Publication 65566.5.1 - October 1996
Figure 4.24
Example
Logic to Generate a BCD Fault Number
| +–FBC––––––––––––––––––––––+ |
| Enable | FILE BIT COMPARE +––(EN)|
+–––] [–––––––––––––––––––+ Source #B168:0 +––(DN)|
| | Reference #B156:0 |––(FD)|
| | Result #N10:0 |––(IN)|
| | Cmp Control R6:0 |––(ER)|
| | Length 160 | |
| | Position 0 | |
| | Result Control R6:1 | |
| | Length 1 | |
| | Position 0 | |
| +––––––––––––––––––––––––––+ |
| |
| Fault Convert Fault |
| Found to BCD for display |
| R6:0 +–TOD––––––––––––––+ |
+–––] [––––––––––––––––––––––––+–––––+ TO BCD +–––|
| 08 | | Source N10:0 | |
| | | Dest D9:0 | |
| | +––––––––––––––––––+ |
| | |
| | Fault |
| | Light |
| | O:013 |
| +––––––––––––––––––––( )––––|
| 01 |
Important: In the FBC instruction above, B156:0 is a 10-word file
cleared to zero. R6:0/09 (IN) is set for single-fault detection.
For additional information on the FBC instruction, refer to the
instruction set documentation for your programming software.
If you need to shorten presets of internal timers, do this in program
file 15. For each timer that you want to change, add a rung as
follows (Figure 4.25):
• input instruction = GEQ (greater than or equal to)
Source A is the address of the timer whose preset you want to change.
Source B is the new preset (base = .01 sec)
• output instruction = Bit address associated with the timer
For example, the following example shortens the timeout value for
Clutch A Failed to Turn OFF from 1 second to 1/2 second.
Figure 4.25
Example
Logic to Shorten a T imer Preset
| +–GEQ––––––––––––––––––––––+ |
| | Greater Than or Equal To | B152 |
+––+ Source A T162:43.ACC +––––––––––––––––––––( )––|
| | Source B 50 | 43 |
| +––––––––––––––––––––––––––+ |
Programming Shorter
Presets for Your
Internal Timers