Publication 1747-RM001G-EN-P - November 2008
A-14 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History
coordinate a timed sequence of events among multiple processors on
the network.
• DF1 radio modem channel 0 driver
This driver implements a protocol, optimized for use with radio modem
networks, that is a hybrid between DF1 Full-duplex protocol and DF1
Half-duplex protocol, and therefore is not compatible with either of
these protocols.
Like DF1 Full-duplex protocol, DF1 Radio Modem allows any node to
initiate to any other node at any time (if the radio modem network
supports full-duplex data port buffering and radio transmission collision
avoidance). Like DF1 Half-duplex protocol, a node ignores any packets
received that have a destination address other than its own, with the
exception of broadcast packets and passthru packets.
Unlike either DF1 Full-duplex or DF1 Half-duplex protocols, DF1
Radio Modem protocol does not include ACKs, NAKs, ENQs, or poll
packets. Data integrity is ensured by the CRC checksum.
• DF1 channel-to-channel passthru
Channel 0 DF1-to-Channel 1 passthru on the SLC 5/04 and 5/05
processors can work with the DF1 Half-duplex Master and DF1 Radio
Modem drivers, in addition to the DF1 Full-duplex driver. The S:34/5
Status File bit is used to enable DF1 passthru functionality for the
channel 0 DF1 Half-duplex Master and DF1 Radio Modem drivers, as
well as for the DF1 Full-duplex driver. For the SLC 5/05 processor, a
Passthru Routing Table must also exist and be configured before
channel-to-channel passthru can occur.
• SLC 5/05 embedded web server capability
SLC 5/05 processors with OS501, Series C, FRN 6 (or higher) includes
the data table memory map, data table monitor screen, and
user-provided web pages via Ethernet using a standard web browser.
In order to view the web server main menu from a standard web
browser, type in http://www.xxx.yyy.zzz for the web address, where
www.xxx.yyy.zzz is the IP address of the SLC 5/05 processor.
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