ARM Cortex-M0 User Manual

Preface
xii Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
About this book
This book is for the Cortex-M0 processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This book is written to help:
• system designers, system integrators, and verification engineers
• software developers who want to use the processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to the processor and its features.
Chapter 2 Functional Description
Read this chapter for a functional overview of the processor and its
components.
Chapter 3 Programmers Model
Read this chapter for an overview of the processor register set, modes of
operation, and other information for programming the processor.
Chapter 4 System Control
Read this chapter for a summary of the system control registers and
programmers model.
Chapter 5 Nested Vectored Interrupt Controller
Read this chapter for a summary of the Nested Vectored Interrupt
Controller (NVIC) registers and programmers model.
Chapter 6 Debug
Read this chapter for a summary of the debug registers and programmers
model.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent