EasyManuals Logo

ARM Cortex-M0 User Manual

ARM Cortex-M0
68 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #48 background imageLoading...
Page #48 background image
Nested Vectored Interrupt Controller
5-2 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
5.1 About the NVIC
External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.
Software can set the priority of each interrupt. The NVIC and the Cortex-M0 processor
core are closely coupled, providing low latency interrupt processing and efficient
processing of late arriving interrupts.
All NVIC registers are only accessible using word transfers. Any attempt to read or
write a halfword or byte individually is Unpredictable.
NVIC registers are always little-endian. Processor accesses are correctly handled
regardless of the endian configuration of the processor.
Processor exception handling is described in Exceptions on page 3-12.
5.1.1 SysTick timer option
The implementation can include a 24-bit SysTick system timer, that extends the
functionality of both the processor and the NVIC.
When present, the NVIC part of the extension provides:
a 24-bit system timer (SysTick)
additional configurable priority SysTick interrupt.
See the ARMv6-M ARM for more information.
5.1.2 Low power modes
The implementation can include a WIC. This enables the processor and NVIC to be put
into a very low-power sleep mode leaving the WIC to identify and prioritize interrupts.
The processor fully implements the Wait For Interrupt (
WFI
), Wait For Event (
WFE
) and
the Send Event (
SEV
) instructions. In addition, the processor also supports the use of
SLEEPONEXIT, which causes the processor core to enter sleep mode when it returns
from an exception handler to Thread mode. See the ARMv6-M ARM for more
information.

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex-M0 and is the answer not in the manual?

ARM Cortex-M0 Specifications

General IconGeneral
ArchitectureARMv6-M
Data Bus Width32-bit
Clock SpeedUp to 50 MHz
InterruptsNested Vectored Interrupt Controller (NVIC)
Number of Cores1
Memory ProtectionOptional Memory Protection Unit (MPU)
Interrupt ControllerNested Vectored Interrupt Controller (NVIC)
Pipeline3-stage
Max Clock Speed50 MHz
Instruction SetThumb
Power ConsumptionLow power design
DebugSerial Wire Debug (SWD)
Die SizeImplementation dependent

Related product manuals