ARM Cortex-M0 User Manual

ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. A-1
ID112415 Non-Confidential
Appendix A
Revisions
This appendix describes the technical changes between released issues of this book.
Table A-1 Issue A
Change Location Affects
First Release - -
Table A-2 Differences between issue A and issue B
Change Location Affects
Update to the product documentation information
Product documentation, design flow and
architecture on page 1-6
All revisions
Update to the instruction set summary Instruction set summary on page 3-4 All revisions
Clarification of the processor core register set summary Processor core registers summary on
page 3-11
All revisions

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent