ARM Cortex-M0 User Manual

Functional Description
2-4 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
2.2 Interfaces
This section describes the external interface functions.
This manual does not include pinout and signal naming because each device
implementation can be different. See the Cortex-M0 Integration Manual or your
implementers documentation for more information.
2.2.1 AHB-Lite interface
Transactions on the AHB-Lite interface are always marked as non-sequential. For
information about the supported transactions, see the Cortex-M0 Integration Manual.
Processor accesses and debug accesses share the external interface to external AHB
peripherals. The processor accesses take priority over debug accesses.
Any vendor specific components can populate this bus.
2.2.2 Debug Access Port
The processor has a low gate count Debug Access Port (DAP). This provides a Serial
Wire or JTAG debug-port, and connects to the processor slave port to provide full
system-level debug access.
You can configure the processor slave port to connect to a full CoreSight DAP system,
with the processor providing full multiprocessor debug simultaneous halt and release
cross-triggering capabilities.
For more information on:
• DAP, see the ADI v5.1 version of the ARM Debug Interface v5, Architecture
Specification
• CoreSight DAP, see the ARM CoreSight Components Technical Reference
Manual.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent