Functional Description
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 2-3
ID112415 Non-Confidential
This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant
exception model that enables the use of pure C functions as interrupt
handlers.
— Low power sleep-mode entry using Wait For Interrupt (
WFI
), Wait For
Event (
WFE
) instructions, or the return from interrupt sleep-on-exit feature.
• NVIC that features:
— 1, 2, 4, 8, 16, 24, or 32 external interrupt inputs, each with four levels of
priority
— dedicated Non-Maskable Interrupt (NMI) input
— support for both level-sensitive and pulse-sensitive interrupt lines
— optional Wake-up Interrupt Controller (WIC), providing ultra-low power
sleep mode support.
• Optional debug support:
— Zero to four hardware breakpoints.
— Zero to two watchpoints.
— Program Counter Sampling Register (PCSR) for non-intrusive code
profiling, if at least one hardware data watchpoint is implemented.
— Single step and vector catch capabilities.
— Support for unlimited software breakpoints using
BKPT
instruction.
— Non-intrusive access to core peripherals and zero-waitstate system slaves
through a compact bus matrix. A debugger can access these devices,
including memory, even when the processor is running.
— Full access to core registers when the processor is halted.
— Optional, low gate-count CoreSight compliant debug access through a
Debug Access Port (DAP) supporting either Serial Wire or JTAG debug
connections.
• Bus interfaces:
— single 32-bit AMBA-3 AHB-Lite system interface that provides simple
integration to all system peripherals and memory
— single 32-bit slave port that supports the DAP.
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