ARM Cortex-M0 User Manual

ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. v
ID112415 Non-Confidential
Contents
Cortex-M0 Technical Reference Manual
Preface
About this book ............................................................................................. xii
Feedback ...................................................................................................... xv
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Features ...................................................................................................... 1-3
1.3 Interfaces .................................................................................................... 1-4
1.4 Configurable options ................................................................................... 1-5
1.5 Product documentation, design flow and architecture ................................ 1-6
1.6 Product revisions ........................................................................................ 1-9
Chapter 2 Functional Description
2.1 About the functions ..................................................................................... 2-2
2.2 Interfaces .................................................................................................... 2-4
Chapter 3 Programmers Model
3.1 About the programmers model .................................................................... 3-2
3.2 Modes of operation and execution .............................................................. 3-3
3.3 Instruction set summary .............................................................................. 3-4
3.4 Memory model ............................................................................................ 3-9
3.5 Processor core registers summary ........................................................... 3-11

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent