ARM Cortex-M0 User Manual

Introduction
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 1-3
ID112415 Non-Confidential
1.2 Features
The processor features and benefits are:
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware multiplier
• deterministic, high-performance interrupt handling for time-critical applications
• Serial Wire Debug reduces the number of pins required for debugging.
For information about Cortex-M0 architectural compliance, see the Architecture and
protocol information on page 1-8.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent