ARM Cortex-M0 User Manual

Introduction
1-8 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
Note
This manual refers to implementation-defined features that can be included by selecting
the appropriate build configuration options. Reference to a feature that is included
means the appropriate build and pin configuration options have been selected.
References to an enabled feature means one that has also been configured by software.
1.5.3 Architecture and protocol information
The processor complies with, or implements, the specifications described in:
• ARM architecture
• Advanced Microcontroller Bus Architecture
• Debug Access Port architecture.
This TRM complements architecture reference manuals, architecture specifications,
protocol specifications, and relevant external standards. It does not duplicate
information from these sources.
ARM architecture
The processor implements the ARMv6-M architecture profile. See the ARMv6-M ARM.
Advanced Microcontroller Bus Architecture
The system bus of the processor implements AMBA-3 AHB-Lite. See the ARM AMBA
3 AHB-Lite Protocol Specification.
Debug Access Port architecture
The Debug Access Port (DAP) is an optional component, defined by v5.1 of the ARM
Debug interface specification, see the ARM Debug Interface v5 Architecture
Specification.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent