ARM Cortex-M0 User Manual

Programmers Model
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 3-11
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3.5 Processor core registers summary
Table 3-3 shows the processor core register set summary. Each of these registers is 32
bits wide.
Note
See the ARMv6-M ARM for information about the processor core registers and their
addresses, access types, and reset values.
Table 3-3 Processor core register set summary
Name Description
R0-R12 R0-R12 are general-purpose registers for data operations.
MSP (R13) The Stack Pointer (SP) is register R13. In Thread mode, the CONTROL
register indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer
(PSP).
PSP (R13)
LR (R14) The Link Register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions.
PC (R15) The Program Counter (PC) is register R15. It contains the current program address.
PSR The Program Status Register (PSR) combines:
• Application Program Status Register (APSR)
• Interrupt Program Status Register (IPSR)
• Execution Program Status Register (EPSR).
These registers provide different views of the PSR.
PRIMASK The PRIMASK register prevents activation of all exceptions with configurable priority. For
information about the exception model the processor supports, see Exceptions on page 3-12.
CONTROL The CONTROL register controls the stack used when the processor is in Thread mode.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent