ARM Cortex-M0 User Manual

Debug
6-6 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
6.1.3 Data watchpoint unit
The Cortex-M0 DWT implementation provides zero, one or two watchpoint register
sets. A processor configured with zero watchpoint implements no watchpoint
functionality and the ROM table shows that no DWT is implemented.
DWT functionality
The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the ARMv6-M ARM.
DWT CoreSight identification
Table 6-4 shows the DWT identification registers and values for debugger detection.
See the ARMv6-M ARM and the ARM CoreSight Components Technical Reference
Manual for more information about the DWT CoreSight identification registers, and
their addresses and access types.
Table 6-4 DWT identification values
Register Value Description
Peripheral ID4
0x00000004 Component and Peripheral ID register formats in the ARMv6-M ARM
Peripheral ID0
0x0000000A
Peripheral ID1 0x000000B0
Peripheral ID2 0x0000000B
Peripheral ID3 0x00000000
Component ID0 0x0000000D
Component ID1 0x000000E0
Component ID2 0x00000005
Component ID3 0x000000B1

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent