To Next Page

To Previous Page

Programmers Model

ID112415 Non-Confidential

3.2 Modes of operation and execution

See the ARMv6-M Architecture Reference Manual for information about the modes of

operation and execution.

Note

Other ARM architectures support the concept of privileged or unprivileged software

execution. This processor does not support different privilege levels. Software

execution is always privileged, meaning software can access all the features of the

processor.

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex-M0 and is the answer not in the manual?

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent